View S3C72M5_5016500.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 1 1 product overview overview the S3C72M5/c72m7/c72m9 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core, sam47 ( samsung arrangeable microcontrollers). with an up-to- 1280 -dot lcd direct drive capability , segment expandable circuit , 8-bit and 16-bit timer/counter, and serial i/o, the S3C72M5/c72m7/c72m9 offers an excellent design solution for a wide variety of applications which require lcd func tions. up to 51 pins of the 1 28 -pin qfp package can be dedicated to i/o. nine vectored interrupts provide fast response to internal and external events. in addi tion, the S3C72M5/c72m7/c72m9 's advanced cmos technology pro vides for low power consumption and a wide oper at ing volta ge range. otp the S3C72M5/c72m7/c72m9 microcontroller is also available in otp (one time programmable) version, s3p72m9. s3p72m9 microcontroller has an on-chip 32-kbyte one-time-programmable eprom instead of masked rom. the s3p72m9 is comparable to S3C72M5/c72m7/c72m9, both in function and in pin configuration except rom size.
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 2 features summary memory ? 3,584 4-bit ram (excluding lcd display ram) ? 16,384/24,576/32 , 768 8-bit rom 51 i/o pins ? i/o: 47 pins (32 pins are configurable as seg pins) ? input only: 4 pins lcd controller/driver ? 80 seg 16 com, 88 seg 8 com terminals ? internal resistor circuit for lcd bias ? 16 level lcd contrast control (software) ? segment expandable circuit ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watch-dog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider 16-bit timer/counter ? programmable 16-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? configurable as two 8-bit timers ? serial i/o interface clock generator watch timer ? time interval generation: 0.5 s, 3.9 ms at 32 , 768 hz ? 4 frequency outputs to buz pin ? clock source generation for lcd 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable ? internal or external clock source comparator ? 3 channel mode: internal reference (4-bit resolution) ? 2 channel mode: external reference interrupts ? f ive internal vectored interrupts ? four external vectored interrupts ? two quasi-interrupts bit sequential carrier ? supports 16-bit serial data transfer in arbitrary format memory-mapped i/o structure ? data memory bank 15 power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system clock stops) ? subsystem clock stop mode oscillation sources ? crystal, c eramic or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 0.4 ? 6 mhz ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8 or 64) instruction execution times ? 0.67, 1.33, 10.7 s at 6 mhz ? 0.95, 1.91, 15.3 s at 4.19 mhz ? 122 s at 32.768 khz operating temperature ? ? 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v package type ? 128-pin qfp
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 3 function overview sam47 cpu all ks57-series microcontrollers have the advanced sam47 cpu core. the sam47 cpu can directly address up to 32 k bytes of program memory. the arithmetic logic unit (alu) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. cpu registers program counter a 1 5- bit program counter (pc) stores addresses for instruction fetches during program execution. usually, the pc is incremented by the number of bytes of the fetched instruction. the one instruction fetch that does not increment the pc is the 1-byte ref instruction which references instructions stored in a look-up table in the rom. whenever a reset operation or an interrupt occurs, bits pc1 3 through pc0 are set to the vector address. stack pointer an 8-bit stack pointer (sp) stores addresses for stack operations. the stack area is located in general-purpose data memory bank 0. the sp is 8-bit read/ writeable and sp bit 0 must always be logical zero. during an interrupt or a subroutine call, the pc value and the psw are written to the stack area. when the service routine has completed, the values referenced by the stack pointer are restored. then, the next instruction is executed. the stack pointer can access the stack despite data memory access enable flag status. since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00h. this sets the first register of the stack area to data memory location 0ffh. program memory in its standard configuration, the 16,384/24,576/32,768 8-bit rom is divided into four areas: ? 16-byte area for vector addresses ? 96-byte instruction reference area ? 16-byte general-purpose area (0010 ? 001fh) ? 16,256/24,448/32,640 -byte area for general-purpose program memory the vector address area is used mostly during reset operations and interrupts. these 16 byte s can alternately be used as general-purpose rom. the ref instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020h ? 007fh. ref can also reference three-byte instructions such as jp or call. so that a ref instruction can reference these instructions, however, the jp or call must be shortened to a 2-byte format. to do this, jp or call is written to the reference area with the format tjp or tcall instead of the normal instruction name. unused locations in the ref instruction look-up area can be allocated to general-purpose use.
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 4 data memory overview the 3,584- bit data memory has five areas: ? 32 ? 4-bit working register area ? 224 ?4 -bit general-purpose a rea in bank 0 which is also used as the stack area ? 256 ?4 -bit general-purpose area in bank 1 , bank 2, ? ? , bank 13, respectively ? 2 56 5 -bit area for lcd data in bank 14 ? 128 ?4-bit area in bank 15 for memory-mapped i/o addresses the data memory area is also organized as sixteen memory banks ? bank 0, bank 1, ? .., and bank 15. you use the select memory bank instruction (smb) to select one of the banks as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. after a hardware reset, data memory initialization values must be defined by program code. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, ? .., or 15. when the emb flag is logical zero, only locations 00h ? 7fh of bank 0 and bank 15 can be accessed. when the emb flag is set to logical one, all sixteen data memory banks can be accessed based on the current smb value. working registers the ram's working register area in data memory bank 0 is also divided into four register banks. each register bank has eight 4-bit registers. paired 4-bit registers are 8-bit addressable. register a can be used as a 4-bit accumulator and double register ea as an 8-bit extended accumulator; double registers wx, wl and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for main programs and banks 1, 2 , and 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 14 . register locations that are not used to store lcd data can be assigned to general-purpose use. bit sequential carrier the bit sequential carrier (bsc) is a 16-bit general register that you can manipulate using 1-, 4- , and 8-bit ram control instructions. using the bsc register, addresses and bit locations can be specified sequentially using 1-bit indirect address ing instructions. in this way, a program can generate 16-bit data output by moving the bit location sequentially, incrementing or decrementing the value of the l register. you can also use direct addressing to manipulate data in the bsc.
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 5 control registers program status word the 8-bit program status word (psw) controls alu operations and instruction execution sequencing. it is also used to restore a program's execution environment when an interrupt has been serviced. program instructions can always address the psw regardless of the current value of data memory access enable flags. before an interrupt is processed, the psw is pushed onto the stack in data memory bank 0. when the routine is completed, psw values are restored. is1 is0 emb erb c sc2 sc1 sc0 interrupt status flags (is1, is0), the enable memory bank and enable register bank flags (emb, erb), and the carry flag (c) are 1 - and 4-bit read/write or 8-bit read-only addressable. skip condition flags (sc0 ? sc2) can be addressed using 8-bit read instructions only. select bank (sb) register two 4-bit locations called the sb register store address values used to access specific mem ory and register banks: the select memory bank register, smb, and the select register bank register, srb. 'smb n' instructions select a data memory bank (0, 1, ? .., or 15) and store the upper four bits of the 12-bit data memory address in the smb register. the 'srb n' instruction is used to select register bank 0, 1, 2, or 3, and to store the address data in the srb. the instructions 'push sb' and 'pop sb' move smb and srb values to and from the stack for interrupts and subroutines. clock circuits main system and subsystem oscillation circuits generate the internal clock signals for the cpu and peripheral hardware. the main system clock can use a c rystal, c eramic, or rc oscillation source, or an externally- generated clock signal. the subsystem clock requires either a crystal oscillator or an external clock source. bit settings in the 4 -bit power control and system clock mode registers select the oscillation source, the cpu clock, and the clock used during power-down mode. the internal system clock signal ( fxx) can be divided inter- nally to produce four cpu clock frequencies ? fx/4, fx/8, fx/64, or fxt/4. interrupts interrupt requests may be generated internally by on-chip processes (intb, intt0, intt1, and ints) or externally by peripheral devices (int0, int1, int4 , and intk). there are two quasi-interrupts: int2 and intw. int2 detects rising or falling edges of incoming signals and intw detects time intervals of 0.5 sec onds or 3.91 milliseconds. the following components support interrupt processing: ? interrupt enable flags ? interrupt request flags ? interrupt priority registers ? power-down termination circuit
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 6 power down to reduce power consumption, there are two power-down modes: idle and stop. the idle instruction initiates idle mode and the stop instruction initiates stop mode. in idle mode, only the cpu clock stops while peripherals and the oscillation source continue to operate normally. stop mode effects only the main system clock ? a subsystem clock, if used, continues oscil lating. in stop mode, main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. reset or an interrupt can be used to terminate either idle or stop mode. reset when a reset signal occurs during normal operation or during power-down mode, the cpu enters idle mode when the reset operation is initiated. when the standard oscillation stabilization interval (31.3?ms at 4.19 mhz) has elapsed, normal cpu operation resumes. i/o ports the S3C72M5/c72m7/c72m9 has 1 3 i/o ports. pin addresses for all i/o ports are mapped in bank 15 of the ram. there are 4 input pins and 47 configurable i/o pins for a to tal of 51 i/o pins. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. timers and timer/counters the timer function has four main components: an 8-bit basic interval timer, an 8-bit timer/counter, a 16-bit timer/counter and a watch timer. the 8-bit basic timer generates interrupt requests at precise intervals, based on the selected clock fre quency and has watch-dog timer function . the programmable 8-bit and 16-bit timer/counters are used for external event counting, generation of arbitrary clock frequencies for output, and dividing external clock signals. the 16 -bit timer/counter is the source of the clock signal that is required to drive the serial i/o interface and configurable as two 8-bit timer/counters . the watch timer has an 8-bit watch timer mode register, a clock selector and a frequency divider circuit. its functions include real-time and watch-time measurement, clock generation for the lcd controller and frequency outputs for buzzer sound.
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 7 lcd driver/controller the S3C72M5/c72m7/c72m9 can directly drive an up-to- 1,280 -dot lcd panel. the lcd function block has the following components: ? ram area for storing display data ? 80 segment output pins (seg0 ? seg 79 ) ? segment expandable circuit ? 16 common output pins (com0 ? com15) ? 5 operating power su pply pins (v lc1 ? v lc5 ) ? sixteen level lcd contrast control circuit (software) frame frequency, lcd clock, duty, and segment pins used for display output are controlled by bit set tings in the 8-bit mode register, lmod. you use the 4-bit lcd control register, lcon, to turn the lcd display on and off, and to control current supplied to the dividing resistors. segment data are output using a direct memory access method synchronized with the lcd frame frequency (f lcd ). using the main system clock, the lcd panel operates in idle mode; during stop mode, it is turned off. if a subsystem clock is used as a clock source, the lcd panel will continue to operate during stop and idle modes. serial i/o interface the serial i/o interface supports the transmission or reception of 8 -bit serial data with an external device. the serial interface has the following functional components: ? 8-bit mode register ? clock selector circuit ? 8-bit buffer register ? 3-bit serial clock counter the serial i/o circuit can be set either to transmit-and-receive or to receive-only mode. msb-first or lsb-first transmis sion is also selectable. the serial interface operates with an internal or an external clock source, or using the clock signal generated by the 16 -bit timer/counter. to modify transmission frequency, the appropriate bits in the serial i/o mode register (smod) must be manipulated. comparator port 4 can be used as a analog input port for a comparator. the reference voltage for the 3-channel comparator can be supplied either internally or externally at p4.2. the comparator module has the following components: ? comparator ? internal reference voltage generator (4-bit resolution) ? external reference voltage source at p4.2 ? comparator mode register (cmod) ? comparison result register (cmpreg)
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 8 block diagram m/p2.0 lcdfr/p2.1 cl/p3.0/tclo0 v lc1 -v lc5 com0-com7 com8-com15/ seg87-seg80 seg0-seg47 seg48-seg79/ port13-port6 program status word flags arithmetic and logic unit instruction decoder internal interrupts interrupt control block stack pointer program counter clock cin0/p4.0 cin1/p4.1 cin2/p4.2 16/24/32 kbit program memory 3,584 x 4-bit data memory seg79/k4/p6.0 seg78/k5/p6.1 seg77/k6/p6.2 seg76/k7/p6.3 seg78-seg72/ p7.0-p7.3 reset xt out xt in x out x in p0.0/ sck/ k0 p0.1/so/k1 p0.2/si/k2 seg71-seg68/ p8.0-p8.3 seg67-seg64/ p9.0-p9.3 sck /k0/p0.0 so/k1/p0.1 si/k2/p0.2 buz/k3/p0.3 basic timer wachdog timer 8-bit timer/ counter1a 8-bit timer/ counter1b int0/p1.0 int1/p1.1 int2/p1.2 int4/p1.3 m/p2.0 lcdfr/p2.1 clo1/p2.2 clo2/p2.3 tclo0/cl/p3.0 tclo1/p3.1 tcl0/p3.2 tcl1/p3.3 seg63-seg60/ p10.0-p10.3 seg59-seg56/ p11.0-p11.3 seg55-seg52/ p12.0-p12.3 seg51-seg48/ p13.0-p13.3 i/o port 3 i/o port 4 i/o port 2 input port 1 i/o port 0 i/o port 7 i/o port 6 i/o port 9 i/o port 8 i/o port 11 i/o port 10 i/o port 13 i/o port 12 segment expander 8-bit timer/ counter0 16-bit timer/ counter1 watch timer lcd driver/ controller comparator serial i/o figure 1-1 . S3C72M5/c72m7/c72m9 simplified block diagram
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 9 pin assignments seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48/p13.3 seg49/p13.2 seg50/p13.1 seg51/p13.0 seg52/p12.3 seg53/p12.2 seg54/p12.1 seg55/p12.0 seg56/p11.3 seg57/p11.2 com9/seg86 com8/seg87 com7 com6 com5 com4 com3 com2 com1 com0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/m p2.1/lcdfr p2.2/clo1 p2.3/clo2 p3.0/tclo0/cl p3.1/tclo1 p3.2/tcl0 S3C72M5/c72m7/c72m9/p72m9 (128-qfp-1420) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p3.3/tcl1 p4.0/cin0 p4.1/cin1 p4.2/cin2 seg79/p6.0/k4 seg78/p6.1/k5 seg77//p6.2/k6 seg76/p6.3/k7 seg75/p7.0 seg74/p7.1 seg73/p7.2 seg72/p7.3 seg71/p8.0 seg70/p8.1 seg69/p8.2 seg68/p8.3 seg67/p9.0 seg66/p9.1 seg65/p9.2 seg64/p9.3 seg63/p10.0 seg62/p10.1 seg61/p10.2 seg60/p10.3 seg59/p11.0 seg58/p11.1 seg85/com10 seg84/com11 seg83/com12 seg82/com13 seg81/com14 seg80/com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 figure 1-2 . S3C72M5/c72m7/c72m9 128-qfp pin assignment
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 10 pin descriptions table 1- 1. S3C72M5/c72m7/c72m9 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. 4-bit unit pull-up resisters are assignable to input pins by software and are automatically disabled for output pins. each bit pin can be allocated as input or output (1-bit unit). the n-ch open drain or push-pull output may be selected by software (1-bit unit). 16 17 18 19 sck /k0 so/k1 si/k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 4 -bit unit pull-up resistors are assignable to input pins by software . 28 29 30 31 int0 int1 int2 int4 p2.0 p2.1 p2.2 p2. 3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. i/o function is s ame as port 0. 32 33 34 35 m lcdfr clo1 clo2 p 3.0 p3.1 p3.2 p3.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. i/o function is s ame as port 0. 36 37 38 39 tclo0/cl tclo1 tcl0 tcl1 p 4 .0 p 4 .1 p 4 .2 i/o 3-bit i/o port. i/o function is same as port 0 except that port 4 is 3-bit i/o port. 40 41 42 cin0 cin1 cin2 p6.0 p6.1 p6.2 p6.3 p7.0 ? p7.3 i/o 4-bit i/o port. 1-, 4-bit and 8-bit read/write and test is possible. 4-bit unit pull-up resisters are assignable to input pins by software and are automatically disabled for output pins . each bit pin can be allocated as input or output (1-bit unit). the n-ch open drain or push- pull output may be selected by software (4-bit unit). 43 44 45 46 47 ? 50 k4/seg79 k5/seg78 k6/seg77 k7/seg76 seg75 ? 72 p8.0 ? p8.3 p9.0 ? p9.3 i/o 4-bit i/o port. 1-, 4-bit and 8-bit read/write and test is possible. i/o function is s ame as port 6, 7. 51 ? 54 55 ? 58 seg 71 ? 68 seg 67 ? 64 p10.0 ? p10.3 p11.0 ? p11.3 i/o 4-bit i/o port. 1-, 4-bit and 8-bit read/write and test is possible. i/o function is s ame as port 6, 7. 59 ? 62 63 ? 66 seg 63 ? 60 seg 59 ? 56 p12.0 ? p12.3 p13.0 ? p13.3 i/o 4-bit i/o port. 1-, 4-bit and 8-bit read/write and test is possible. i/o function is s ame as port 6, 7. 67 ? 70 71 ? 74 seg 55 ? 52 seg 51 ? 48 sck i/o serial i/o interface clock signal 16 p0.0 so i/o serial data output 17 p0.1 si i/o serial data input 18 p0.2 buz i/o 2, 4, 8 , 16 khz frequency output for buzzer sound 19 p0.3 k0 ? k3 k4 ? k7 i/o external interrupts with rising/falling edge detection 16 ? 19 43 ? 46 p0.0 ? p0.3 p6.0 ? p6.3
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 11 table 1- 1. S3C72M5/c72m7/c72m9 pin descriptions (continued) pin name pin type description number share pin int0 i external interrupts with rising/falling edge detection 28 p1.0 int1 i external interrupts with rising/falling edge detection 29 p1.1 int2 i external quasi-interrupts with rising/falling edge detection 30 p1.2 int4 i external interrupts with rising/falling edge detection 31 p1.3 m i/o alternated signal for seg driver 32 p2.0 lcdfr i/o synchronous frame signal for seg driver 33 p2.1 clo1 i/o clock output or operating clock for seg driver 34 p2.2 clo 2 i/o clock output or operating c lock for seg driver 35 p2.3 cl i/o data shift clock for seg driver 36 p3.0 tclo0 i/o timer/counter0 clock output 36 p3.0 tclo1 i/o timer/counter 1 clock output 37 p3.1 tcl0 i/o external clock input for timer/counter 0 38 p3.2 tcl1 i/o external clock input for timer/counter 1 39 p3.3 cin0 ? cin2 i/o cin0,1: comparator input only cin2: comparator input or external reference input 40, 41 42 p4.0 ? p4.1 p4.2 seg0 ? seg 47 o lcd segment data output 122 ? 75 ? seg4 8 ? seg 79 o lcd segment data output 74 ? 43 port13 ? 6 seg 80 ? seg 8 7 o lcd segment data output 2,1, 128 ? 123 com15 ? 8 com0 ? com7 o lcd common data output 10 ? 3 ? com8 ? com15 o lcd common data output 123 ? 128 1, 2 seg87 ? 80 v lc1 ? v lc5 ? lcd power supply . voltage dividing resistors are fixed. 15 ? 11 ? v dd ? main power supply 20 ? v ss ? ground 21 ? x in , x out ? crystal, c eramic , or rc oscillator signal i/o for main system clock. 23, 22 ? x t in , xt out ? crystal oscillator signal i/o for subsystem clock. 25, 26 ? test i test signal input (must be connected to v ss ) 24 ? reset i reset signal 27 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
product overview S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 1 - 12 table 1- 2. overview of S3C72M5/c72m7/c72m9 pin data pin names share pins i/o type reset value circuit type p0.0 ? p0.3 sck , so, si, buz/ k0 ? k3 i/o input e-2 p1.0 ? p1. 3 int0 ? int2 , int4 i input a- 3 p2.0 ? p2. 3 m, lcdfr, clo1, clo2 i/o input e p3.0 ? p3.1 tclo0 /cl , tclo1 i/o input e p3.2 ? p3.3 tcl0, tcl1 i/o input e-1 p4.0 ? p4.2 cin0 ? cin2 i/o input f-4 p6.0 ? p6.3 k4 ? k7 /seg79 ? seg76 i/o input h-15 p7.0 ? p7.3 seg 75 ? seg 72 i/o input h-8 p8.0 ? p8.3 seg 71 ? seg 68 i/o input h-8 p9.0 ? p9.3 seg 67 ? seg 64 i/o input h-8 p 10 .0 ? p 10 .3 seg 63 ? seg 60 i/o input h-8 p 11 .0 ? p 11 .3 seg 59 ? seg 56 i/o input h-8 p 12 .0 ? p 12 .3 seg 55 ? seg 52 i/o input h-8 p 13 .0 ? p 13 .3 seg 51 ? seg 48 i/o input h-8 com0 ? com7 ? o low output h-4 com 8 ? com 15 seg 87 ? seg 80 o low output h-6 seg0 ? seg 47 ? o low output h-5 v lc1 ? v lc5 ? ? ? ? v dd ? ? ? ? v ss ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? reset ? i ? b test ? i ? ?
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 13 pin circuit diagrams schmitt trigger pull-up resistor v dd resistor enable in p-channel figure 1-3 . pin circuit type a-3 in pull-up resistor v dd schmitt trigger figure 1-4. pin circuit type b n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1-5. pin circuit type e schmitt trigger n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1-6. pin circuit type e-1
product overview S3C72M5/c72m7/c72m 9/p72m9 ( preliminary spec ) 1 - 14 schmitt trigger n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1-7 . pin circuit type e-2 n-ch v dd i/o pne p-ch output disable data schmitt trigger resistor enable v dd pull-up resistor + - ext-ref (p4.2 only) analog in digital in comparator int-ref digital or analog selectable by software (p4mod) figure 1-8 . pin circuit type f-4
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) product overview 1 - 15 out v lc1 v lc2 com v ss v lc5 figure 1-9 . pin circuit type h-4 out v lc1 v lc3 seg v ss v lc4 figure 1- 1 0 . pin circuit type h-5 out seg/com v lc2 v lc3 v lc1 v lc5 v lc4 v ss figure 1- 1 1 . pin circuit type h-6 out v ss v lc4 seg v lc1 v lc3 output disable figure 1-12. pin circuit type h-7
product overview S3C72M5/c72m7/c72m 9/p72m9 ( preliminary spec ) 1 - 16 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch data circuit type h-7 seg output disable 2 output disable 1 pne figure 1-13. pin circuit type h-8 n-ch v dd resistor enable v dd i/o pull-up resistor p-ch data circuit type h-7 seg output disable 2 output disable 1 pne schmitt trigger figure 1-14. pin circuit type h-15
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 1 1 5 electrical data overview in this section, information on S3C72M5/c72m7/c72m9 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? comparator electrical characteristics ? lcd contrast controller characteristics ? a.c. electrical characteristics ? o perating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a.c timing measurement point s ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl 0/tcl1 timing ? input timing for reset signal ? input timing for external interrupts and quasi-interrupts ? serial data transfer timing
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o pins active ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 2 ? 9 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 4, 6, p3.2, p3.3, and reset 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ? 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 ? v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 4, 6, p3.2, p3.3, and reset 0.2 v dd v il3 x in , x out , xt in , and xt out 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 m a ports 0, 2 , 3, 4, ports 6 ? 13 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0, 2 , 3, 4, ports 6 ? 13 ? ? 2.0 v v dd = 1.8 v to 5.5 v i ol = 1.6 ma 0.4
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 3 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i = 0 v all input pins except reset , x in , x out , xt in , and xt out ? ? ? 3 a i lil2 v i = 0 v reset , x in , x out , xt in , and xt out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-up resistor r l i v i = 0 v; v dd = 5 v port s 0 ? 4, ports 6 ? 13 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 250 400 v dd = 3 v 200 500 800 lcd voltage dividing resistor r lcd ? 40 60 90 k w | v lc1 -com i | voltage drop (i = 0 ? 15) v dc ? 15 a per common pin ? ? 120 mv | v lc1 -segx| voltage drop (x = 0 ? 79 ) v ds ? 15 a per segment pin ? ? 120 v lc 2 output voltage v lc 2 v dd = 1.8 v to 5.5 v , 1/5 bias lcd clock = 0 hz, v lc 1 = v dd 0.8 v dd ? 0.2 0.8 v dd 0.8 v dd ? 0.2 v v lc 3 output voltage v lc 3 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd ? 0.2 v lc 4 output voltage v lc 4 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd ? 0.2 v lc 5 output voltage v lc 5 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd ? 0.2
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 4 table 15- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current ( 1 ) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.9 2.9 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.8 1.3 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 .3 30 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents . 2 . data includes power consumption for subsystem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 5 table 15- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillato r clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range ; v dd = 3.0 v. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 2. 7 v to 5 .5 v ? ? 10 ms v dd = 1.8 v to 5 .5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency r = 2 0 k w , v dd = 5 v ? 2 ? mhz r = 39 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in i nput frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 6 table 15- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5 .5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs.
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 7 table 15- 5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 15-6 . comparator electrical characteristics (t a = ? 40 c + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage internal v cin1 ? ? ? 150 mv accuracy external v cin2 ? ? ? 150 mv input leakage current i cin , i ref ? ? 3 ? 3 m a table 15-7 . lcd contrast controller characteristics (t a = ? 40 c + 85 c, v dd = 4.5 v to 5.5 v ) parameter symbol condition min typ max units resolution ? ? ? ? 4 bits linearity rlin ? ? ? 1.0 lsb max output voltage (lcnst = #8fh) v lpp v lc1 =v dd =5v 4.9 ? v lc1 v
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 8 table 15-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5 .5 v 0.95 64 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 1.8 v to 5 .5 v 1 tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v ; input 800 ? ? ns output 650 v dd = 1.8 v to 5 .5 v ; input 3200 output 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v ; input 325 ? ? ns output t kcy /2 ? 50 v dd = 1.8 v to 5 .5 v ; input 1600 output t kcy / 2 ? 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v ; input 100 ? ? ns v dd = 2.7 v to 5.5 v ; output 150 v dd = 1.8 v to 5.5 v ; input 150 v dd = 1.8 v to 5.5 v ; output 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v ; input 400 ? ? ns v dd = 2.7 v to 5.5 v ; output 400 v dd = 1.8 v to 5.5 v ; input 600 v dd = 1.8 v to 5.5 v ; output 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 9 table 15-8 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v ; input ? ? 300 ns v dd = 2.7 v to 5.5 v ; output 250 v dd = 1.8 v to 5.5 v ; input 1000 v dd = 1.8 v to 5.5 v ; output 1000 interrupt input high, low width t inth , t intl int0 , int1, int2, int4, k0 ? k7 10 ? ? s reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting. 1.5 mhz cpu clock 1.05 mhz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 15- 1. standard operating voltage range
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 10 table 15-9. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 15-2. stop mode release timing when initiated by reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 15-3. stop mode release timing when initiated by interrupt request
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 15-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 15-5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 15-6 . clock timing measurement at xt in
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) electrical data 15- 13 tcl0/tcl1 t tih t til 1/f ti 0.7 v dd 0.3 v dd figure 15-7 . tcl 0/tcl1 timing reset t rsl 0.2 v dd figure 15-8 . input timing for reset signal int0, 1, 2, 4, k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 15-9 . input timing for external interrupts and quasi-interrupts
electrical data S3C72M5/c72m7/c72m9 /p72m9 ( preliminary spec ) 15- 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 15- 1 0 . serial data transfer timing
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) mechanical data 16- 1 16 mechanical data overview the S3C72M5/c72m7/c72m9/p72m9 microcontroller is currently available in a 128-pin qfp package. 128-qfp-1420 #128 20.00 0.20 22.00 0.30 14.00 0.20 16.00 0.30 0.15 + 0.10 - 0.05 0-8 0.10 max #1 note : dimensions are in millimeters. (0.75) 0.50 0.20 0.05 min 2.10 0.10 2.40 max 0.50 0.20 0.50 0.20 + 0.10 - 0.05 (0.75) 0.10 max 0.10 max figure 16-1. 128-qfp-1420 package dimensions
mechanical data s3c7 2m5/c72m7/c72m9/p72m9 ( preliminary spec ) 16- 2 notes
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) s3p72m9 otp 17- 1 17 s3p72m9 otp overview the s3p72m9 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C72M5/c72m7/c72m9 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p72m9 is fully compatible with the S3C72M5/c72m7/c72m9, both in function and in pin configuration except rom size. because of its simple programming requirements, the s3p72m9 is ideal for use as an evaluation chip for the S3C72M5/c72m7/c72m9.
s3p72m9 otp S3C72M5/c72m7/c72m 9/p72m9 ( preliminary spec ) 17- 2 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48/p13.3 seg49/p13.2 seg50/p13.1 seg51/p13.0 seg52/p12.3 seg53/p12.2 seg54/p12.1 seg55/p12.0 seg56/p11.3 seg57/p11.2 com9/seg86 com8/seg87 com7 com6 com5 com4 com3 com2 com1 com0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset /reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/m p2.1/lcdfr p2.2/clo1 p2.3/clo2 p3.0/tclo0/cl p3.1/tclo1 p3.2/tcl0 S3C72M5/c72m7/c72m9/p72m9 (128-qfp-1420) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p3.3/tcl1 p4.0/cin0 p4.1/cin1 p4.2/cin2 seg79/p6.0/k4 seg78/p6.1/k5 seg77//p6.2/k6 seg76/p6.3/k7 seg75/p7.0 seg74/p7.1 seg73/p7.2 seg72/p7.3 seg71/p8.0 seg70/p8.1 seg69/p8.2 seg68/p8.3 seg67/p9.0 seg66/p9.1 seg65/p9.2 seg64/p9.3 seg63/p10.0 seg62/p10.1 seg61/p10.2 seg60/p10.3 seg59/p11.0 seg58/p11.1 seg85/com10 seg84/com11 seg83/com12 seg82/com13 seg81/com14 seg80/com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 note: the bold indicate an otp pin name. figure 17-1. s3p72m9 pin assignments (128-qfp package)
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) s3p72m9 otp 17- 3 table 17-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 18 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 19 i/o serial clock pin. input only pin. test v pp (test) 24 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 27 i chip initialization v dd /v ss v dd /v ss 20/21 i logic power supply pin. v dd should be tied to +5 v during programming. table 17-2. comparison of s3p72m9 and S3C72M5/c72m7/c72m9 features characteristic s3p72m9 S3C72M5/c72m7/c72m9 program memory 32-kbyte eprom 16/24/32-kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, vpp (test) = 12.5v pin configuration 128 qfp 128 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72m9, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 17-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
s3p72m9 otp S3C72M5/c72m7/c72m 9/p72m9 ( preliminary spec ) 17- 4 start address = first location v dd = 5 v, v pp = 12.5 v x = 0 program one 1 ms pulse increment x v dd = v pp = 5 v compare all byte device passed pass verify 1 byte last address fail no increment address x = 10 no yes verify byte fail fail device faild figure 17-2. otp programming algorithm
S3C72M5/c72m7/c72m9/p72m9 ( preliminary spec ) s3p72m9 otp 17- 5 table 17-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current (1) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.9 2.9 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.8 1.3 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 .3 30 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents . 2 . data includes power consumption for subsystem clock os cillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
s3p72m9 otp S3C72M5/c72m7/c72m 9/p72m9 ( preliminary spec ) 17- 6 1.5 mhz cpu clock 1.05 mhz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 17-3 . standard operating voltage range

▲Up To Search▲

Price & Availability of S3C72M5

	To Download S3C72M5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .